Design of Finite Impulse Response Filter Architecture using Wallace Tree Multipliers


  • Ravichandran S



Low power multiplier, Reversible Logic gates, Digital circuits, Verilog HDL.


Finite impulse response (FIR) filter is one of the main key mechanisms in any communication systems. The output of the system is relates to the FIR filter, so need to design an efficient FIR filter, to get a perfect output. Filter design contains many blocks; one of the main blocks is multiplier. Many types of multipliers are available in the digital circuits, but need an efficient multiplier design to get better filters. Multiplier is one of the basic building blocks in the digital circuits. So the performance of the multiplier is important to get an efficient circuit design. Power consumption is one of the major drawbacks in the multiplier. Power consumed by the multiplier is higher in the digital circuits. Wallace tree multiplier was designed and implemented using verilogHDL. This multiplier reduces the stages of partial product addition. So this multiplier takes less number of gates to implement and also it overcomes the existing multiplier drawbacks. Finally the designed multipliers are applied into the FIR filter, and show the best filter.


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Author Biography

Ravichandran S

Pro Vice-Chancellor, Dr.M.G.R. Educational And Research Institute, Maduravoyal, Chennai, Tamilnadu, India.


[1] J. Chen, et al, (2014) “Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System”, IEEE Transaction on Circuits and Systems, Vol. 62, Issue. 1, pp: 1-10.

[2] A. Dandapat, S, et al, (2010) “A 1.2- ns16×16-Bit Binary Multiplier Using High Speed Compressors”, World Academy of Science, Engineering and Technology.

[3] V. Gowrishankar, et al, (2013) “Efficient FIR Filter Design Using Modified Carry Select Adder & Wallace Tree Multiplier” International Journal of Science, Engineering and Technology Research (IJSETR), Vol. 2, Issue. 3, pp: 703-711.

[4] T. Hentschel and G. Fettweis,(1999) “Software radio receivers,” in CDMA Techniques for Third Generation Mobile Systems. Dordrecht, The Netherlands: Kluwer, pp. 257–283.

[5] Jagadeshwar Rao M and Sanjay Dubey, (2012) “A High Speed Wallace Tree Multiplier Using Modified Booth Algorithm for Fast Arithmetic Circuits”, IOSR Journal of Electronics and Communication Engineering, vol. 3, no. 1.

[6] C. U. Kumar, and B. J. Rabi,(2014) “Area efficient FIR filter using graph based algorithm”, In Current Trends in Engineering and Technology (ICCTET), 2nd International Conference, pp: pp. 495-498, IEEE.

[7] X. Lai, and Z. Lin,(2014) “Optimal Design of Constrained FIR Filters Without Phase Response Specifications”, IEEE Transactions on signal processing, Vol.62, Issue. 7, pp: 4532-4546. [8] M.Moris Mano,(2002) “Digital Design”, Pearson Education, 3rd edition.