• Nivedha M
  • Priyadharshini V
  • Rathi Meena K
Keywords: Mutiply-Accumulator (MAC), Digital Signal Processing (DSP), Vedic Multiplier, Square Root Carry Select Adder (SQRT CSLA), Carry Select Adder (CSLA), Booth Multiplier, Wallace Tree Multiplier.


The Multiply-Accumulate unit is the main computational kernel in Digital Signal Processing application. To determine the speed of the entire hardware systems, the Multiply and Accumulate Unit (MAC) always play an important role. The efficient MAC Unit is used to support the variable precisions and parallel functions with high desirability. In this work, 64 Bit MAC Design using area efficient Vedic Multiplier and Square Root Carry-Select Adder (SQRT CSLA) for DSP Processors is implemented. To design a N*N Vedic MAC Design, four N/2*N/2 Vedic Multiplier and Square Root Carry Select Adder are required for an efficient design. Various adders such as Ripple Carry Adder, Carry Save Adder, Square root Carry Select Adder and multipliers such as Booth Multiplier, Wallace Tree Multiplier and Vedic Multiplier are analyzed. Conventional MAC design is implemented using Vedic Multiplier with Ripple Carry Adder (RCA). To reduce the Look-Up Tables (LUTs), Delay and Power, the Vedic Multiplier with Square Root Carry Select Adder (SQRT CSLA) is proposed in this work. The Conventional and Proposed MAC design are coded in Verilog HDL Language, synthesized using Xilinx ISE and simulated using Modelsim XE. Number of LUT Counts, Delay and Power of the conventional MAC and Proposed MAC are compared.


Download data is not yet available.

Author Biographies

Nivedha M

B.E (ECE), Associate Professor (ECE) SSN College Of Engineering, Chennai, Tamil Nadu- 603110.

Priyadharshini V

B.E (ECE), Associate Professor (ECE) SSN College Of Engineering, Chennai, Tamil Nadu- 603110.

Rathi Meena K

B.E (ECE), Associate Professor (ECE) SSN College Of Engineering, Chennai,
Tamil Nadu- 603110.


[1] Abdelgawad, A. and Bayoumi, M. (2007) ―High speed and area efficient Multiply Accumulate Unit (MAC) for Digital Signal Processing applications‖, Proc. IEEE Int. symp. Circuits Syst. (ISCAS), pp. 3199-3202.

[2] Marimuthu, C.N. and Thiangaraj, P. (2008) ―Low Power High Performance Multiplier‖, ICGST-PDCS, Vol.8.

[3] Raghunath, R.K.J. et al. (1997) ―A compact carry-save multiplier architecture and its applications‖,Proc. IEEE 40th Midwest Symp. Circuits and Systems, Vol.2, pp. 794-797.

[4] Elguibaly, F. (2000) ―A fast parallel multiplier-accumulator using the modified Booth algorithm‖, IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, pp. 902-098.

[5] Senthilpari, C. Ajay Kumar Singh, and Diwadkar, K. (2007) ―Low power and high speed 8x8 bit Multiplier Using Non-clocked Pass Transistor Logic‖, IEEE, Vol.9/07, pp.1-4244- 1355.

[6] Tam Anh Chu, (2002) ―Booth Multiplier with Low Power High Performance Input Circuitary‖, US Patent, B1.6.393.454 .

[7] Wallace, C.S. (1964) ―A suggestion for a fast multiplier‖, IEEE Transactions on Electronic Computers, Vol.13, No.1, pp. 14–17.50

[8] Raghunath, R.K. Et al. (1997) ―A compact carry-save multiplier architecture and its applications,‖ Proc. IEEE 40th Midwest Symp. Circuits and Systems, vol. 2, pp. 794-797.

[9] Ohsang Kwon, Nowka, K and Swartzlander, E.E. (2000) ―A 16-bitx16-bit MAC design using fast 5:2 compressors,‖ Proc. Of IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 235 –243.

[10] Ayman Fayed, Walid Elgharbawy, and Magdy Bayoumi, (2004) ―A merged Multiply accumulate for high-speed signal processing application,‖ ICASSP IEEE.

[11] Law, C.F, Rofail, S.S, and Yeo, K.S. (1999)―A Low-Power 16×16-Bit Parallel Multiplier Utilizing Pass-Transistor Logic‖ IEEE Journal of Solid State circuits, Vol.34, No.10, pp. 1395-1399.

[12] Wallace, C.S. (1967) ―A Suggestion for a fast multipliers,‖ IEEE Trans. Electronic Computers, vol. 13, no.l, pp 14-17.

[13] Tiwari, Gankhuyag, G. and Kim, C.M. and Cho, Y.B. (2008) ―Multiplier design based on ancient Indian Vedic mathematics‖, Proc. Int SoC Design Conf., pp.65-68.

[14] Ramkumar. B and Kittur, H.M, (2012) ―Low-power and area-efficient Carry select adder,‖ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.20, no. 2, pp. 371–375.