A Novel Architecture Based DWT with Folded and Pipelined Schemes for Infrasound Signal Classification
Infrasound is a low frequency acoustic phenomenon that typically ranges from 0.01 to 20 Hz. The data collected from infrasound microphones are presented online by the infrasound monitoring system operating in Northern Europe. Processing the continuous flow of data to extract optimal feature information is important for real-time signal classification. Performing wavelet decomposition on the real-time signals is an alternative. In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied in the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speed up the clock rate of the DWT. Our approach uses only two FIR filters, a high-pass and a low-pass filter. A compact implementation was realized with pipelining techniques and multiple uses of generalized building blocks. The design was described in VHDL and the FPGA implementation and simulation were performed on the Xilinx ISE
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