BIST-BASED GROUP TESTING FOR DIAGNOSIS OF EMBEDDED FPGA CORES

  • Sendhil Kumar N C
Keywords: Embedded Cores, SOPC, FPGA Testing, Group Testing, DSP Hard Cores.

Abstract

A group testing-based BIST technique to identify faulty hard cores in FPGA devices is presented. The method provides for isolation of faults in embedded cores as demonstrated by experiments on the Virtex-5 family of Xilinx FPGAs. High-level HDL code is developed to instantiate a Finite State Machine (FSM) which generates the test inputs for the Blocks Under Test (BUTs). The BUTs are divided into groups of four and at the end of a single stage of testing, up to 2 faulty BUTs are isolated successfully in each group of four. Experiments conducted show efficient fault isolation with a maximum of 30% area overhead under testing conditions. Isolation of faulty DSP cores is rapidly achieved without any permanent area cost. The approach can be readily extended to other embedded cores such as Block RAMs and Multipliers, thus providing a fast, efficient technique for testing prior to System On a Programmable Chip (SoPC) implementation on state of the art SRAM FPGAs.

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Author Biography

Sendhil Kumar N C

Assistant Professor Department of ECE Ranipettai Engineering college Vellore, India.

References

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Published
2009-12-20
Section
Articles