Design of an FFT/IFFT Processor for MIMO OFDM Systems

  • Raman c K
  • Madhusudhanan R
Keywords: 80211n, fast Fourier transform (FFT), multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM).

Abstract

In this paper, we present a novel 128/64 point fast Fourier transform (FFT)/ inverse FFT (IFFT) processor for the applications in a multiple-input multiple- output orthogonal frequency-division multiplexing based IEEE 802.11n wireless local area network baseband processor. The unfolding mixed-radix multipath delay feedback FFT architecture is proposed to efficiently deal with multiple data sequences. The proposed processor not only supports the operation of FFT/IFFT in 128 points and 64 points but can also provide different throughput rates for 1–4 simultaneous data sequences to meet IEEE 802.11n requirements. Furthermore, less hardware complexity is needed in our design compared with traditional four-parallel approach. The proposed FFT/IFFT processor is designed in a 0.13- m single-poly and eight-metal CMOS process. The core area is an FFT/IFFT processor and a test module. At the operation clock rate of 40 MHz, our proposed processor can calculate128-point FFT with four independent data sequences within 3.2 μs meeting IEEE 802.11n standard requirements.

Downloads

Download data is not yet available.

Author Biographies

Raman c K

Assistant Professor, Department of ECE,PSR Engineering College, Sivakasi Tamil nadu.

Madhusudhanan R

Research scholar,Sathyabama university, Chennai.

References

1. Mujtaba et al., TGn Sync Proposal Tech.Specification for IEEE 802.11 Task Group 2005, IEEE 802.11-04/0889r3.

2. S. Magar, S. Shen, G. Luikuo, M. Fleming, and R. Aguilar, “An application specific DSP chip set for 100-MHz data rates,”in Proc. Int. Conf. Acoustics, Speech, Signal Process., Apr. 1988, vol. 4, pp. 1989–1992.

3. H. Shousheng and M. Torkelson, “Designing pipeline FFT processor for OFDM (de)modulation,” in Proc. URSI Int. Symp. on Signals, Syst, Electron., Oct. 1998, vol. 29, pp. 257–262.

4. J. O’Brien, J. Mather, and B. Holland, “A 200 MIPS single-chip 1 k FFT processor,” in Proc. IEEE Int. Solid- State Circuits Conf., 1989, vol. 36, pp. 166–167,, 327.

5. B. M. Bass, “A low-power, high-performance, 1024-point FFT processor,” IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 380–387, Mar. 1999.

6. W.-C. Yeh and C.-W. Jen, “High-speed and low- power split-radix FFT,” IEEE Trans. Acoust., Speech, Signal Process., vol. 51, no. 3, pp. 864–874, Mar. 2003.

7. Y.-W. Lin, H.-Y. Liu, and C.-Y. Lee, “A 1 GS/s FFT/IFFT processor for UWB applications,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1726–1735, Aug. 2005.

8. L. Jia, Y. Gao, J. Isoaho, and H. Tenhunen, “A new VLSI- oriented FFT algorithm and implement,” in Proc. 11th Annual IEEE Int. ASIC Conf., Sep. 1998, pp. 337–341.

9. A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1999.

10. E. E. Swartzlander, W. K. W. Young, and S. J. Joseph, “A radix 4 delay commutator for fast fourier transform processor implementation,” IEEE J. Solid-State Circuits, vol. 19, no. 10, pp. 702–709, Oct. 1984.

11. L. R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1975.
Published
2009-12-20
Section
Articles