FPGA based Digital Pulse Width Modulator with Time Resolution under 2 ns

  • Murugesan R
  • Madhusudhanan R

Abstract

This work proposes a new DPWM architecture that takes advantage of FPGA’s advanced characteristics, especially the DLLs (Delay-Locked Loop) present in almost every FPGA. The proposed DPWM combines a synchronous (counter-based) block with an asynchronous block for increased resolution without unnecessarily increasing the clock frequency. The experimental results show an implementation in a low cost FPGA (Xilinx Spartan-3) that uses an external 32 MHz clock for a final time resolution under 2 ns.

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Author Biographies

Murugesan R

Assistant Professor, Department of EEE,Ranipettai Engineering college , vellore,Tamilnadu,India.

Madhusudhanan R

Research scholar

References

1. IEEE Trans. Power Electron. (Special Issue on Digital Control in Power Electronics), vol. 18, n. 1, part II, Jan. 2003.

2. B. J. Patella, A. Prodic, A. Zirger, D. Maksimovic, “High-Frequency Digital Controller IC for DC-DC Converters”, IEEE Trans. Power Electron., vol. 18, n. 1, pp. 438-446, Jan. 2003.

3.A. V. Peterchev, J. Xiao, S. R. Sanders, “Architecture and IC Implementation of a Digital VRM Controller”, IEEE Trans. Power Electron., vol. 18, n. 1, pp. 356-364, Jan. 2003.

4. A. V. Peterchev, S. R. Sanders, “Quantization Resolution and Limit Cycling in Digitally Controlled PWM Converters”, IEEE Trans. Power Electron., vol. 18, n. 1, pp. 301-308, Jan. 2003.

5.H. Peng, A. Prodic, E. Alarcon, D. Maksimovic, "Modeling of Quantization Effects in Digitally Controlled DC-DC Converters", Proc. IEEE Power Electronics Specialists Conf. (PESC), Jun. 2004, Aachen, Germany, pp. 4312-4318.

6. A.P. Dancy, A.P. Chandrakasan, “Ultra low power control circuits for PWM converters”, Proc. IEEE Power Electronics Specialists Conf. (PESC), June 1997, St. Louis, Missouri, USA, vol. 1, pp. 21-27.

7. E. O'Malley, K. Rinne, "A Programmable Digital Pulse Width Modulator Providing Versatile Pulse Patterns and Supporting Switching Frequencies Beyond 15 MHz", Proc. IEEE Applied Power Electronics Conf. Expo (APEC), vol. 1, Feb. 2004, Anaheim, CA, pp. 53-59.
Published
2009-12-20
Section
Articles