FPGA based Digital Pulse Width Modulator with Time Resolution under 2 ns

  • Murugesan R
  • Madhusudhanan R


This work proposes a new DPWM architecture that takes advantage of FPGA’s advanced characteristics, especially the DLLs (Delay-Locked Loop) present in almost every FPGA. The proposed DPWM combines a synchronous (counter-based) block with an asynchronous block for increased resolution without unnecessarily increasing the clock frequency. The experimental results show an implementation in a low cost FPGA (Xilinx Spartan-3) that uses an external 32 MHz clock for a final time resolution under 2 ns.


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Author Biographies

Murugesan R

Assistant Professor, Department of EEE,Ranipettai Engineering college , vellore,Tamilnadu,India.

Madhusudhanan R

Research scholar


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