Low Power Dissipation and High Fault Coverage Fault Emulation of Synchronous Sequential Circuits on FPGA

  • Madhusudhanan R
Keywords: LT-RTPG, 3-weight WRBIST, fault simulation.


A feasibility study of accelerating fault simulation by emulation on field programmable gate arrays (FPGAs) is described. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated with fault simulation of sequential circuits are explained. Alternatives that can be considered as trade-offs in terms of the required FPGA resources and accuracy of test quality assessment are discussed. In addition, an extension to the existing environment for re-configurable hardware emulation of fault simulation is presented. It incorporates hardware support for fault dropping. This paper presents a low hardware overhead test pattern generator (TPG) for Fault Emulation that can reduce switching activity in circuits under test (CUTs) during testing and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed test pattern generation decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed method is comprised of two TPGs: LT-RTPG and 3- weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT- RTPG patterns are applied. The proposed approach allows simulation speed-up of 40–500 times as compared to the state-of-the-art in software-based fault simulation. On the basis of the experiments, it can be concluded that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors while using simple but flexible algorithmic test vector generating circuits, for example built-in self-test.


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Author Biography

Madhusudhanan R

Research scholar, Sathyabama University, Chennai, India


1. Bardell, P. H., W. H. McAnney, and J. Savir, “Built-In Test for VLSI: Pseudorandom Techniques”, New York: Wiley, 1987.

2. Hellebrand, S., J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, “Built-In test for circuits with scan based on reseeding of multiple polynomial linear feedback shift registers,” IEEE Trans. Comput., vol.44, no. 2, pp. 223–233,1995.

3. Zacharia, N., J. Rajski, and J. Tyszer, “Decompression of test data using variable-length seed LFSRs”, in Proc. IEEE 13th VLSI Test Symp., pp. 426–433, 1995.

4. Hellebrand, S., S. Tarnick, and J. Rajski, “Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift registers,” in Proc. IEEE Int. Test Conf., pp. 120– 129, 1992.

5. Touba, N. A, and E. J. McCluskey, “Altering a pseudo-random bit sequence for scan-based BIST”, in Proc. IEEE Int. Test Conf.,pp.167–175, 1996.

6. Chatterjee, M, and D. K. Pradhan, “A new pattern biasing technique for BIST”, in Proc. VLSITS, pp. 417–425, 1995.

7. Tamarapalli, N, and J. Rajski, “Constructive multi-phase test point insertion for scan-based BIST”, in Proc. IEEE Int. Test Conf, pp. 649–658, 1996.

8. Savaria, Y., B. Lague, and B. Kaminska, “A pragmatic approach to the design of self-testing circuits”, in Proc. IEEE Int. Test Conf., pp.745–754, 1989.

9. Hartmann, J, and G. Kemnitz, “How to do weighted random testing for BIST”, in Proc. IEEE Int. Conf. Comp. - Aided Design, pp. 568–571, 1993.

10. Waicukauski, J., E. Lindbloom, E.Eichelberger, and O. Forlenza, “A method for generating weighted random test patterns”, IEEE Trans. Comp., vol. 33, no. 2, pp. 149–161, 1989.

11. Tsai, H.C., K.T. Cheng, C.J. Lin, and S. Bhawmik, “Efficient test point selection for scan-based BIST”, IEEE Trans. VLSI System, vol. 6, no. 4, pp. 667–676, 1998.

12. Li, W., C. Yu, S. M. Reddy, and I. Pomeranz, “A scan BIST generation method using a markov source and partial BIST bit-fixing”, in Proc. IEEE-ACM Design Autom. Conf, pp.554–559, 2003.

13. Basturkmen, N. Z., S. M. Reddy, and I. Pomeranz, “Pseudo random patterns using markov sources for scan BIST”, in Proc. IEEE Int. Test Conf., 2002, pp. 1013–1021.

14. Zorian, Y. “A distributed BIST control scheme for complex VLSI devices”, in Proc. VLSI Testing Symp., pp. 4–9, 1993.

15. Golomb, S. W., “Shift Register Sequences. Laguna Hills”, CA: Aegean Park, 1982.

16. Tsui, C.Y., M. Pedram, C.A. Chen, and A. M. Despain, “Low power state assignment targeting two-and multi-level logic implementation”, in Proc. IEEE Int. Conf. Comput.-Aided Des., pp. 82–87, 1994.

17. Girard, P., L. Guiller, C. Landrault, and S. Pravossoudovitch, “A test vector inhibiting technique for low energy BIST design”, in Proc. VLSI Test. Symp., pp. 407–412, 1999.

18. Dabholkar, V., S. Chakravarty, I. Pomeranz, and S. Reddy, “Techniques for minimizing power dissipation in scan and combinational circuits during test application”, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst, vol. 17, no. 12, pp.1325–1333,1998.

19. Chou, R. M., K. K. Saluja, and V. D. Agrawal, “Scheduling tests for VLSI systems under power constraints,” IEEE Trans. VLSI Syst., vol. 5, no. 2, pp. 175–185, 1997.