DESIGN OF FIR FILTER USING DIFFERENT MULTIPLIER ARCHITECTURE FOR HIGH SPEED AND LOW POWER APPLICATIONS
Finite impulse response (FIR) filter is one of the key components in any DSP and communication systems. The output from the DSP processor is based on the FIR filter performance, so need an efficient FIR filter design, to achieve an efficient output. FIR Filter architecture contains many components; one of the key components is multiplier. Different types of multipliers are available in the digital circuits, but need an efficient multiplier design to get efficient filters. In the existing Vedic and Wallace tree multiplier was designed and implemented using verilogHDL. Partial products generation and reduction in the Wallace tree multiplier getting more complicated in speed and performance and also multiplier needs more gates to implement the design. To reduce the drawbacks in the existing system, to propose a new efficient multiplier named as Birecoder multiplier. It is one of the best multiplier in the digital circuit design. This multiplier overcomes the existing multiplier drawbacks by using multiplexer circuit. Multiplier is design by verilogHDL, after the design Wallace tree multiplier is compared with Birecoder, and analyzes the performance of the multiplier. Implement the design using Modelsim 6.3c and Xilinx ISE. Finally the designed multipliers are applied into the FIR filter, and show the best filter.
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