DESIGN OF LOW POWER AND AREA EFFICIENT SRAM ARCHITECTURE BASED ON GDI TECHNIQUE

  • Jeyasree C
Keywords: 5T SRAM Cell, Power Dissipation, Delay, Cell area

Abstract

Semiconductor memories are most important subsystem of modern digital systems. In new era the scaling of silicon technology has been ongoing, due to scaling large memory can be fabricated on a single chip as results memories are capable to store and retrieve large amount of information at high speed. But due to high density, power dissipation gets increases and speed decreases. So there is need for the design of low power and high speed circuit in memory. Here presents a new five transistor (5T) CMOS and Fin FET SRAM cell to accomplish improvements in stability, power dissipation, and performance over previous designs, for high speed and high stability memory operation. 5T SRAM using low power reduction techniques. All the simulations have been carried out at Tanner EDA tool. In this project, will modify 5T SRAM cell with the use of high threshold PMOS Devices that results in decrease in the leakage that reduces power dissipation. The circuit designing and simulation is done on the Tanner tool, Schematic of the SRAM cell is designed on the S-Edit and net list simulation done by using T-spice and waveforms are analyzed through the W-edit.

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Author Biography

Jeyasree C

PG Scholar, ME Applied Electronics Sri Lakshmi Ammal Engineering College, Chennai.

References

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Published
2017-03-27
Section
Articles